EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 403
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 403 of 478
- Download datasheet (13Mb)
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–4. Write Transaction Waveform—Use ‘logical_channel_address port’ Option
Notes to
(1) In this waveform example, you are writing to only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
© December 2010 Altera Corporation
logical_channel_address port is 2 bits wide.
logical_channel_address [1:0]
Figure
rx_tx_duplex_sel [1:0]
3–4:
tx_vodctrl [2:0]
Figure 3–4
Read Transaction
For example, to read the existing V
the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG
instance, perform the following steps:
1. Set the logical_channel_address input port to the logical channel address of the
2. Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are
3. Ensure that the busy signal is low before you start a read transaction.
4. Assert the read signal for one reconfig_clk clock cycle. This initiates the read
The busy output status signal is asserted high to indicate that the dynamic
reconfiguration controller is busy reading the PMA control values. When the read
transaction has completed, the busy signal goes low. The data_valid signal is asserted
to indicate that the data available at the read control signal is valid.
reconfig_clk
transceiver channel whose PMA controls you want to read (for example,
tx_vodctrl_out).
read from the transceiver channel.
transaction.
write_all
busy
(2)
(1)
shows the write transaction waveform for Method 1.
3'b111
2'b00
2'b00
OD
values from the transmit V
3'b001
2'b10
2'b01
Cyclone IV Device Handbook, Volume 2
OD
control registers of
3–13
Related parts for EP4CGX15BF14C8N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: