EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 388
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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2–22
Simulation Requirements
Reference Information
Cyclone IV Device Handbook, Volume 2
The following are simulation requirements:
■
■
■
■
■
For more information about some useful reference terms used in this chapter, refer to
the links listed in
Table 2–7. Reference Information
Dynamic Reconfiguration Reset Sequences
The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port
is not instantiated, you must assert the tx_digitalreset, rx_digitalreset,
and rx_analogreset signals appropriately for correct simulation behavior.
If the gxb_powerdown port is instantiated, and the other reset signals are not
used, you must assert the gxb_powerdown signal for at least 1 s for correct
simulation behavior.
You can deassert the rx_digitalreset signal immediately after the
rx_freqlocked signal goes high to reduce the simulation run time. It is not
necessary to wait for t
The busy signal is deasserted after about 20 parallel reconfig_clk clock cycles
in order to reduce simulation run time. For silicon behavior in hardware, you can
follow the reset sequences described in the previous pages.
In PCIe mode simulation, you must assert the tx_forceelecidle signal for at
least one parallel clock cycle before transmitting normal data for correct
simulation behavior.
Non-Bonded channel configuration
Bonded channel configuration
Terms Used in this Chapter
rx_digitalreset
tx_digitalreset
Automatic Lock Mode
rx_analogreset
gxb_powerdown
rx_freqlocked
Manual Lock Mode
pll_locked
pll_areset
Table
busy
PCIe
LTD
LTR
2–7.
LTD_Auto
(as suggested in the actual reset sequence).
Chapter 2: Cyclone IV Reset Control and Power Down
Useful Reference Points
© December 2010 Altera Corporation
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Simulation Requirements
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