EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 316
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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1–36
Figure 1–38. Transmitter Only Datapath Clocking in Bonded Channel Configuration
Cyclone IV Device Handbook, Volume 2
tx_coreclk[3]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[0]
Fabric
FPGA
coreclkout
1
When the byte serializer is enabled, the common bonded low-speed clock frequency is
halved before feeding to the read clock of TX phase compensation FIFO. The common
bonded low-speed clock is available in FPGA fabric as coreclkout port, which can
be used in FPGA fabric to send transmitter data and control signals to the bonded
channels.
Bonded channel configuration is not available for Receiver Only channel operation
because each of the channels are individually clocked by its recovered clock.
For Transmitter and Receiver operation in bonded channel configuration, the receiver
PCS supports configuration with rate match FIFO, and configuration without rate
match FIFO.
operation with rate match FIFO in ×2 and ×4 bonded channel configurations. For
Transmitter and Receiver operation in bonded channel configuration without rate
match FIFO, the datapath clocking is identical to
transmitter channels, and
/2
Figure 1–39
wr_clk
wr_clk
wr_clk
wr_clk
Tx Phase
Tx Phase
Tx Phase
Tx Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
rd_clk
rd_clk
rd_clk
rd_clk
shows the datapath clocking in Transmitter and Receiver
Figure 1–34 on page 1–31
wr_clk
wr_clk
wr_clk
wr_clk
Byte Serializer
Byte Serializer
Byte Serializer
Byte Serializer
Transmitter Channel PCS 3
/2
Transmitter Channel PCS 2
/2
Transmitter Channel PCS 1
/2
Transmitter Channel PCS 0
/2
rd_clk
rd_clk
rd_clk
rd_clk
Figure 1–38
Chapter 1: Cyclone IV Transceivers Architecture
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
for the receiver channels.
© December 2010 Altera Corporation
for the bonded
Transceiver Clocking Architecture
In 2 Bonded Channel Configuration
Transmitter Channel PMA 3
Transmitter Channel PMA 2
Transmitter Channel PMA 1
Transmitter Channel PMA 0
In 4 Bonded Channel Configuration
Serializer
Serializer
Serializer
Serializer
low-speed clock
high-speed
clock
high-speed
clock
high-speed
clock
high-speed
clock
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