EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 78
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EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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5–16
Figure 5–8. clkena Implementation: Output Enable
PLLs in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
clkin
clkena
clk_out
f
1
1
The clkena circuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in
Figure 5–8
signal is sampled on the falling edge of the clock (clkin).
This feature is useful for applications that require low power or sleep mode.
The clkena signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
Altera recommends using the clkena signals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by de-asserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
3. Allow some clock cycles of the secondary clock to pass before reasserting the
Cyclone IV GX devices offer two variations of PLLs: general purpose PLLs and
multipurpose PLLs. Cyclone IV E devices only have the general purpose PLLs.
The general purpose PLLs are used for general-purpose applications in the FPGA
fabric and periphery such as external memory interfaces. The multipurpose PLLs are
used for clocking the transceiver blocks. When the multipurpose PLLs are not used
for transceiver clocking, they can be used for general-purpose clocking.
For more details about the multipurpose PLLs used for transceiver clocking, refer to
the
block.
clkena signal. The exact number of clock cycles you must wait before enabling
the secondary clock is design-dependent. You can build custom logic to ensure
glitch-free transition when switching between different clock sources.
Cyclone IV Transceivers
shows the waveform example for a clock output enable. The clkena
chapter.
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
PLLs in Cyclone IV Devices
Figure
5–7.
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