EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 227
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Device Configuration Pins
Table 8–16. Configuration Pin Summary for Cyclone IV GX Devices
© December 2010 Altera Corporation
Notes to
(1) The CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain output in the CRC
(2) To tri-state AS configuration pins in the AS configuration scheme, turn on the Enable input tri-state on active configuration pins in user mode
Bank
8
3
9
3
9
9
3
3
9
9
3
9
9
9
9
8
3
3
9
6
6
Error Detection tab of the Device and Pin Options dialog box.
option from the Device and Pin Options dialog box. This tri-states DCLK, nCSO, Data[0], and Data[1]/ASDO pins. Dual-purpose pins
settings for these pins are ignored. To set these pins to different settings, turn off the Enable input tri-state on active configuration pins in
user mode option and set the desired setting from the Dual-purpose Pins Setting menu.
Table
Data[4:2]
Data[7:5]
nCSO
CRC_ERROR
DATA[0]
DATA[1]/ASDO
INIT_DONE
nSTATUS
nCE
DCLK
CONF_DONE
TDI
TMS
TCK
nCONFIG
CLKUSR
nCEO
MSEL
TDO
DEV_OE
DEV_CLRn
8–16:
Description
(2)
(2)
(2)
Table 8–16
configuration related pins on Cyclone IV devices.
device pin configuration for the Cyclone IV GX and Cyclone IV E, respectively.
(2)
through
Input/Output
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Table 8–19
describe the connections and functionality of all the
Dedicated
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
—
V
CCIO
Powered By
Table 8–16
/Pull-up
Pull-up
Pull-up
Pull-up
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CCINT
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
Cyclone IV Device Handbook, Volume 1
(1)
and
Table 8–17
Configuration Mode
Optional, all modes
Optional, all modes
Optional, all modes
PS, FPP, AS
All modes
All modes
All modes
All modes
All modes
Optional
Optional
Optional
PS, FPP
JTAG
JTAG
JTAG
JTAG
FPP
FPP
FPP
AS
AS
AS
list the
8–61
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