EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 201

• Manufacturer Part Number: EP4CGX15BF14C8N
• Description: IC CYCLONE IV FPGA 15K 169FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX15BF14C8N

• Number Of Logic Elements/cells: 14400
• Number Of Labs/clbs: 900
• Total Ram Bits: 540000
• Number Of I /o: 72
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 169-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1475

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Table 8–10. PS Configuration Timing Parameters For Cyclone IV Devices (Part 1 of 2)
© December 2010 Altera Corporation
t
t
t
t
CF2CD
CF2ST0
CFG
STATUS
Symbol
nCONFIG low to
CONF_DONE low
nCONFIG low to
nSTATUS low
nCONFIG low pulse
width
nSTATUS low pulse
width
Parameter
PS Configuration Timing
A PS configuration must meet the setup and hold timing parameters and the
maximum clock frequency. When using a microprocessor or another intelligent host
to control the PS interface, ensure that you meet these timing requirements.
Figure 8–16
host device.
Figure 8–16. PS Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
(2) After power up, the Cyclone IV device holds nSTATUS low during POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more convenient.
(5) Do not leave the DATA[0]pin floating after configuration. Drive the DATA[0]pin high or low, whichever is more
Table 8–10
CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
When using the AS configuration scheme, DCLK is a Cyclone IV device output pin and must not be driven externally.
convenient.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
nCONFIG
DCLK (4)
User I/O
lists the PS configuration timing parameters for Cyclone IV devices.
DATA[0]
shows the timing waveform for PS configuration when using an external
8–16:
Cyclone IV
Tri-stated with internal pull-up resistor
t
t
CFG
CF2CD
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
(2)
Minimum
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
t
CH
500
t
—
—
45
CLK
t
DSU
t
CL
t
Cyclone IV E
DH
(3)
(Note 1)
Cyclone IV
Bit n
(Note 1)
Cyclone IV Device Handbook, Volume 1
(2)
Maximum
230
t
500
500
CD2UM
—
Cyclone IV E
(4)
User Mode
(5)
(3)
Unit
µs
ns
ns
ns
8–35