EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 353
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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Chapter 1: Cyclone IV Transceivers Architecture
Loopback
Loopback
Reverse Parallel Loopback
Figure 1–70. PIPE Reverse Parallel Loopback Path
Note to
(1) Grayed-Out Blocks are Not Active in this mode.
© December 2010 Altera Corporation
Fabric
FPGA
Figure 1–70
Transceiver
1
:
Cyclone IV GX devices provide three loopback options that allow you to verify the
operation of different functional blocks in the transceiver channel. The following
loopback modes are available:
■
■
■
In each loopback mode, all transmitter buffer and receiver buffer settings are available
if the buffers are active, unless stated otherwise.
The reverse parallel loopback option is only available for PIPE mode. In this mode,
the received serial data passes through the receiver CDR, deserializer, word aligner,
and rate match FIFO before looping back to the transmitter serializer and transmitted
out through the TX buffer, as shown in
to the FPGA fabric. This loopback mode is compliant with version 2.00 of the
Interface for the PCI Express Architecture
To enable the reverse parallel loopback mode, assert the tx_detectrxloopback
port in P0 power state.
PCIe
hard
IP
reverse parallel loopback (available only for PIPE mode)
serial loopback (available for all modes except PIPE mode)
reverse serial loopback (available for all modes except XAUI mode)
PIPE
IF
(Note 1)
Rx PCS
Match
Reverse parallel
FIFO
Rate
loopback path
Tx PCS
Figure
specification.
Aligner
1–70. The received data is also available
Word
Tx PMA
Serializer
Cyclone IV Device Handbook, Volume 2
Rx PMA
Deserial-
izer
CDR
PHY
1–73
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