EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 318
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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1–38
Cyclone IV Device Handbook, Volume 2
In configuration with rate match FIFO, the transmitter datapath clocking is identical
to Transmitter Only operation as shown in
channel, the CDR unit recovers the clock from serial received data and generates the
high- and low-speed recovered clock for each bonded channel. The high-speed
recovered clock feeds the channel's deserializer, and low-speed recovered clock is
forwarded to receiver PCS. The individual low-speed recovered clock feeds to the
following blocks in the receiver PCS:
■
■
The common bonded low-speed clock that is used in all bonded transmitter PCS
datapaths feeds the following blocks in each bonded receiver PCS:
■
■
■
■
■
When the byte deserializer is enabled, the common bonded low-speed clock
frequency is halved before feeding to the write clock of RX phase compensation FIFO.
The common bonded low-speed clock is available in FPGA fabric as coreclkout
port, which can be used in FPGA fabric to send transmitter data and control signals,
and capture receiver data and status signals from the bonded channels.
word aligner
write clock of rate match FIFO
read clock of rate match FIFO
8B/10B decoder
write clock of byte deserializer
byte ordering
write clock of RX phase compensation FIFO
Figure
Chapter 1: Cyclone IV Transceivers Architecture
1–38. In each bonded receiver
© December 2010 Altera Corporation
Transceiver Clocking Architecture
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