EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 340
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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1–60
Cyclone IV Device Handbook, Volume 2
Figure 1–61
Figure 1–61. Transceiver Configuration in Serial RapidIO Mode
Lane Synchronization
In Serial RapidIO mode, the word aligner is compliant to the SRIO Specification 1.3
and is configured in automatic synchronization state machine mode with the
parameter settings as listed in
Table 1–20. Synchronization State Machine Parameters
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 10-bit pattern lengths in SRIO mode.
Table
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Data Rate (Gbps)
1–20:
shows the transceiver configuration in Serial RapidIO mode.
Table
Parameter
1–20.
Disabled
62.5/125/
1.25/2.5/
Enabled
Enabled
Chapter 1: Cyclone IV Transceivers Architecture
(Note 1)
16-Bit
156.25
3.125
Automatic Synchronization
State Machine (10-Bit)
Disabled
Enabled
SRIO
×1
© December 2010 Altera Corporation
Disabled
62.5/125/
1.25/2.5/
Disabled
Enabled
156.25
16-Bit
3.125
Transceiver Functional Modes
Value
127
255
3
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