TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 67

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

Chapter 6
Memory Protection Unit (MPU)
6.1
Using the memory protection unit module
6.1.1 Overview
This chapter demonstrates how to use the MPU module, which concurrently monitors
system BUS activities and its access privileges on internal RAM. The following example
shows how to program the region descriptors that define internal RAM memory spaces
and their access rights.
6.1.2 Introduction
The MPU is a Freescale Kinetis module for memory protection. This module should not
be confused with ARM’s MPU. ARM’s MPU is not integrated in Kinetis MCUs.
However, both Freescale and ARM MPU shared the same purposes – regions protection,
access permissions, and overlapping regions protection. In addition, the Freescale MPU
provides access error detection and multiple bus masters monitor.
6.1.3 Features
A Memory Management Unit (MMU) is designed for complex memory management and
memory protection in microprocessors with Translation Look-aside Buffer (TLB),
paging, dynamic allocation, access protection, and virtual memory. This MMU
implementation will be costly for the overall system – it will have a large memory
footprint, higher power consumption, paging segmentation, and larger die size for Kinetis
MCUs.
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
Freescale Semiconductor
67