TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 43

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

In addition to the clocks provided by the MCG, there are three other system level clock
sources available for use by various peripheral modules:
4.3 Configuration examples
The MCG can be configured in one of several modes to provide a flexible means of
providing clocks to the system for a wide range of applications. Some of the more
commonly used modes are described in the following configuration examples.
After exiting reset, or recovering from a very low leakage state, the MCG will be in FLL
engaged internal (FEI) mode with MCGCLKOUT at 20.97 MHz, assuming a factory
trimmed slow IRC frequency of 32.768 kHz. If a different MCG mode is required, the
MCG can be transitioned to that mode under software control.
Although not included in the sample code, you should include a “timeout” mechanism
when checking the status bits within the MCG. After making changes to clock selection
bits, enabling the oscillator or the PLL, the appropriate status bits should be verified
before continuing. If for some reason the bit being checked does not update, the “while
loop” will never exit unless a timeout mechanism is used. A timeout counter should be
started before checking the status bits. This counter must then be stopped and reset after
the loop exits. If a timeout is generated, a decision can be made about what to do
depending on the status bits that failed to update. For example, if the oscillator does not
Freescale Semiconductor
• MCGPLLCLK – this is the output of the PLL and is available any time the PLL is
• MCGIRCLK – this is the output of the selected IRC. The selected IRC will be
• MCGFFCLK – this is either the slow IRC or the external clock source divided by the
• OSCERCLK – this is the clock provided by the system oscillator and is the output of
• ERCLK32K – this is the output of the RTC oscillator or the system oscillator if it is
• LPO – this is the output of the low power oscillator. It is an on-chip, very low power
enabled.
enabled whenever this clock is selected.
FLL external reference divider (FRDIV). This clock is available in all modes except
FLL bypassed internal (FBI) and bypassed low power internal (BLPI) when the slow
IRC is selected. The source of this clock is selected by the value of the internal
reference select bit (IREFS).
the oscillator or the external square wave clock source.
set to provide a 32 kHz clock in low power mode.
oscillator with an output of approximately 1 kHz that is available in all run and low
power modes.
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
Chapter 4 Clocking System
43