TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 42

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TWR-K60N512-KEIL

Manufacturer Part Number
TWR-K60N512-KEIL
Description
K60N512 Keil Tower Kit
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Type
MCUr

Specifications of TWR-K60N512-KEIL

Rohs Compliant
YES
Contents
4 Boards, Documentation, DVD
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Freescale Tower System, K60N512
Features
The system level clocks are provided by the MCG. The MCG consists of:
The clocks provided by the MCG are summarized as follows:
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• Two individually trimable internal reference clocks (IRC), a slow IRC with a
• Frequency locked loop (FLL) using the slow IRC or an external source as the
• Phase locked loop (PLL) using an external source as the reference clock.
• Auto trim machine (ATM) to allow both of the IRCs to be trimmed to a custom
• MCGOUTCLK – this is the main system clock used to generate the core, bus, and
• MCGFLLCLK – this is the output of the FLL and is available any time the FLL is
EXTAL32
XTAL32
frequency of ~32 kHz and a fast IRC with a frequency of ~4 MHz (with a fixed
divide by 2).
reference clock.
frequency using an externally-generated reference clock.
memory clocks. It can be generated from one of the on-chip reference oscillators, the
on-chip crystal/resonator oscillator, an externally generated square wave clock, the
FLL, or the PLL.
enabled.
EXTAL
XTAL
Slow IRC
Fast IRC
OSC
logic
System oscillator
PLL
RTC oscillator
CG — Clock gate
XTAL_CLK
OSC logic
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
Figure 4-1. Clock distribution diagram
OSC32KCLK
FRDIV
OSCCLK
MCG
CG
÷2
FLL
MCGPLLCLK
MCGFLLCLK
CG
MCGOUTCLK
PMC logic
OUTDIV2
OUTDIV3
OUTDIV4
OUTDIV1
PMC
SIM
MCGPLLCLK/
MCGFLLCLK
MCGFFCLK
OSCERCLK
MCGIRCLK
ERCLK32K
CG
CG
CG
CG
LPO
Freescale Semiconductor
Core / system clocks
Bus clock
FlexBus clock
Flash clock
Real-time clock
Clock options for
some peripherals

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