TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 105

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

Chapter 11 Universal Asynchronous Receiver and Transmitter (UART) Module
CPU loading. However, the overhead required to set up the interrupts or DMA should be
taken into account. If the additional overhead outweighs the reduction in CPU loading,
then polling is the best approach.
Using the UART interrupts to signal the CPU that data can be read from or written to the
UART will help to decrease the CPU loading. The UART has a number of status and
error interrupt flags that can be used, but for typical receive and transmit operations the
receive data register full flag (UARTx_S1[RDRF]) and transmit data register empty flag
(UARTx_S1[TDRE]) would be enabled using the UARTx_C2[TIE, RIE] bits. The names
of these flags are a bit misleading, since they don't always indicate a full or empty
condition. For UARTs that include a FIFO, the full or empty condition is determined
based on the amount of data in the FIFO compared to a programmable watermark. If both
the RDRF and TDRE interrupt requests are enabled, then the UART interrupt handler
would need to read the S1 register to determine which condition is true then read and/or
write to the UART data register (UARTx_D) to clear the flags. Since the CPU is still
responsible for moving data there is CPU loading associated with an interrupt-driven
software approach.
Using the DMA to move data can help to decrease the CPU loading even more than using
the UART interrupts. The UART's same RDRF and TDRE flags used for an interrupt-
driven software approach can be re-routed to the DMA controller instead. This is done by
setting the UARTx_C5[TDMAS, RDMAS] bits. Each of these requests would be routed
to a different DMA channel (the specific DMA channels would be selected by
programming the DMA channel mux). One DMA channel would be responsible for
handling receive traffic, so it would read one or more bytes from the UART for each
request. The second DMA channel would be responsible for handling the transmit traffic,
so it would write one or more bytes to the UART for each request. When the entire
transmit or receive DMA movement is complete the DMA can interrupt the core to notify
it of the completion. In this approach the CPU has no loading associated with the actual
data movement. All of the CPU loading is the result of the initial configuration of both
the UART and DMA modules and then any processing of data that is required to prepare
it for transmission or interpret it after reception.
11.4 UART RS-232 hardware implementation
The diagram below shows a block diagram of the hardware connections for an RS-232
implementation. The diagram shows the optional hardware flow control signals, but only
the RX and TX data connections are required.
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
Freescale Semiconductor
105