TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 36

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

Configuration examples
3.2 Configuration examples
The NVIC is easy to configure. Two examples are shown in this section. The first
example shows how to configure the NVIC for a module. The low power timer (LPTMR)
is used as the base for this example. The second example shows how to locate the vector
table from the flash to RAM.
3.2.1 Configuring the NVIC
Configuring the NVIC for the specific module involves writing three registers:
NVICSERx (NVIC Set Enable Register), NVICCPRx (NVIC Clear Pending Register),
and NVICIPxx (NVIC Interrupt Priority). After the NVIC is configured and the desired
peripheral has its interrupts enabled, the NVIC serves any pending request from that
module by going to the module's ISR.
3.2.1.1 Code example and explanation
This example shows how to set up the NVIC for a specific module. In this case the
LPTMR is used.
The steps to configure the NVIC for this module are:
36
Address
ARM Core System Handler Vectors
0x0000_0000
Vector
0
1
2
3
4
5
6
11
12
14
15
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
IRQ
—
—
—
—
—
—
—
—
—
—
—
Table 3-1. Core exceptions
Source module
ARM core
ARM core
ARM core
ARM core
ARM core
ARM core
ARM core
ARM core
ARM core
ARM core
ARM core
Source description
Initial stack pointer
Initial program Counter
NMI
Hard fault
Memory manage fault
Bus fault
Usage fault
SVCall
Debug monitor
Pendable request for system service
System tick timer
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