WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 70

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

4.3.2
Figure 16.
Table 28.
70
Timing Diagram
Power-Up Timing Diagram
Notes to Power-Up Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
PCIe reference clock
Note
Power-On-Reset
Manageability /
PCIe Link up
NVM Load
PHY State
(internal)
D-State
PERST#
Power
Wake
Xosc is stable txog after power is stable
Internal reset is released after all power supplies are good and tppg after Xosc
is stable.
An NVM read starts on the rising edge of the internal reset or Internal Power
On Reset#.
After reading the NVM, PHY might exit power down mode.
APM wake up and/or manageability might be enabled based on NVM contents.
The PCIe reference clock is valid tPWRGD-CLK before the de-assertion of
PE_RST_N (according to PCIe specification).
PE_RST_N is de-asserted tPVPGL after power is stable (according to PCIe
specification).
De-assertion of PE_RST_N causes the NVM to be re-read, asserts PHY power-
down, and disables Wake Up.
After reading the NVM, PHY exits power-down mode.
Link training starts after tpgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-
assertion.
A first PCI configuration response can be sent after tpgres from PE_RST_N de-
assertion
Writing a 1b to the Memory Access Enable bit in the PCI Command register
transitions the device from D0u to D0 state.
Xosc
txo
g
1
Powered-down
tpp
g
tPWRGD
-CLK
2
6
3
tPVP
GL
Read
Auto
4
5
7
tee
Ext.
Conf.
Active / Down
Dr
8
Read
Auto
9
82574 GbE Controller—Initialization
tee
Ext.
Conf.
tpgtrn
10
tpgcfg
11
D0u
tpgres
L0
12
13
D0a