WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 431

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WG82574L S LBA8

Manufacturer Part Number
WG82574L S LBA8
Description
Manufacturer
Intel
Datasheet

Specifications of WG82574L S LBA8

Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Compliant
Design Considerations—82574 GbE Controller
Figure 67.
13.5.5
13.5.5.1
82574 10/100 Mb/s Magnetics Module Connections (With CMC)
Layout Considerations for the Ethernet Interface
These sections provide recommendations for performing printed circuit board layouts.
Good layout practices are essential to meet IEEE PHY conformance specifications and
EMI regulatory requirements.
Critical signal traces should be kept as short as possible to decrease the likelihood of
being affected by high frequency noise from other signals, including noise carried on
power and ground planes. Keeping the traces as short as possible can also reduce
capacitive loading.
Since the transmission line medium extends onto the printed circuit board, special
attention must be paid to layout and routing of the differential signal pairs.
Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100
Mb/s. For the 82574, system level tests should be performed at all three speeds.
Guidelines for Component Placement
Component placement can affect signal quality, emissions, and component operating
temperature This section provides guidelines for component placement.
Careful component placement can:
M o d u le w ith C o m m o n M o d e
• Decrease potential problems directly related to electromagnetic interference (EMI),
• Simplify the task of routing traces. To some extent, component orientation will
C h o ke in B o th R x a n d T x
which could cause failure to meet applicable government test specifications.
affect the complexity of trace routing. The overall objective is to minimize turns and
crossovers between traces.
1 0 /1 0 0 M a g n e tic s
P a th s
LA N _ 1 .9 V
M D I_ P LU S (0 )
M D I_ P LU S (1 )
M D I_ P LU S (2 )
M D I_ P LU S (3 )
M D I_ M IN U S (0 )
M D I_ M IN U S (1 )
M D I_ M IN U S (2 )
M D I_ M IN U S (3 )
R es is to rs
5 0 O hm
5 8
5 7
5 5
5 4
5 3
5 2
5 0
4 9
8 2 5 7 4
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