WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 120

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Figure 23.
7.1.3.1
Note:
7.1.3.2
7.1.3.3
Figure 24.
120
1. The checksum indicated here is the unadjusted 16-bit ones complement of the packet. A software assist might
82574 Legacy Rx Descriptor
Length Field (16-Bit, Offset 0)
Upon receipt of a packet for this device, hardware stores the packet data into the
indicated buffer and writes the length, Packet Checksum, Status, Errors, and Status
fields. Length covers the data written to a receive buffer including CRC bytes (if any).
Software must read multiple descriptors to determine the complete length for packets
that span multiple receive buffers.
Packet Checksum (16-Bit, Offset 16)
For standard 802.3 packets (non-VLAN) the packet checksum is by default computed
over the entire packet from the first byte of the DA through the last byte of the CRC,
including the Ethernet and IP headers. Software can modify the starting offset for the
packet checksum calculation via the Receive Checksum Control register (RXCSUM).
This register is described in
the packet checksum, software must adjust the packet checksum value to back out the
bytes that are not part of the true TCP checksum. When operating with the legacy Rx
descriptor, the RXCSUM.IPPCSE and the RXCSUM.PCSD should be cleared (the default
value).
For packets with VLAN header the packet checksum includes the header if VLAN
striping is not enabled by the CTRL.VME. If VLAN header strip is enabled, the packet
checksum and the starting offset of the packet checksum exclude the VLAN header.
Status Field (8-Bit, Offset 32)
Status information indicates whether the descriptor has been used and whether the
referenced buffer is the last one for the packet.
Receive Status (RDESC.STATUS-0) Layout
Rsvd (bit 7) - Reserved
IPCS (bit 6) - IPv4 checksum calculated on packet
be required to back out appropriate information prior to sending it up to upper software layers. The packet
checksum is always reported in the first descriptor (even in the case of multi-descriptor packets).
0
8
Rsvd
7
VLAN Tag
IPCS
6
63
TCPCS
5
Errors
section
48 47
UDPCS
4
10.2.5.15. To verify the TCP/UDP checksum using
Buffer Address [63:0]
40 39
Status
VP
3
32 31
Packet Checksum
Rsvd
82574 GbE Controller—Inline Functions
2
16 15
EOP
1
1
Length
DD
0
0