WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 331

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Driver Programing Interface—82574 GbE Controller
10.2.5.23
Note:
Note:
Note:
10.2.5.24
Receive Address High - RAH (0x05404 + 8*n; RW)
While "n" is the exact unicast/Multicast address entry and it is equals to 0,1,…15
These registers contain the upper bits of the 48-bit Ethernet address. The complete
address is {RAH, RAL}. AV determines whether this address is compared against the
incoming packet. AV is cleared by a master reset in entries 0-14, and on Internal Power
On Reset in entry 15.
ASEL enables the device to perform special filtering on receive packets.
The first receive address register (RAR0) is also used for exact match pause frame
checking (DA matches the first register). Therefore RAR0 should always be used to
store the individual Ethernet MAC address of the 82574.
These registers' addresses have been moved from where they were located in previous
devices. However, for backwards compatibility, these registers can also be accessed at
their alias offsets of 0x0040-0x000BC.
After reset, if the NVM is present, the first register (Receive Address Register 0) is
loaded from the IA field in the NVM, its Address Select field will be 00b, and its Address
Valid field will be 1b. If no NVM is present the Address Valid field for n=0b will be 0b.
The Address Valid field for all of the other registers is 0b.
The software device driver can use only entries 0-14. Entry 15 is reserved for
manageability firmware usage.
VLAN Filter Table Array - VFTA[127:0] (0x05600-0x057FC; RW)
RAH
ASEL
Reserved
AV
Bit Vector
Field
Field
15:0
17:16
30:18
31
31:0
Bit(s)
Bit(s)
X
X
0x0
X
X
Initial
Initial
Value
Value
Receive Address High
The upper 16 bits of the 48-bit Ethernet address.
Address Select
Selects how the address is to be used. Decoded as follows:
00b = Destination address (must be set to this in normal mode).
01b = Source address.
10b = Reserved.
11b = Reserved.
Reserved
Reads as 0x0. Ignored on write.
Address Valid
Cleared after master reset. If the NVM is present, the Address Valid
field of Receive Address Register 0 are set to 1b after a software or
PCI reset or NVM read.
In entries 0-14 this bit is cleared by master reset. The AV bit of entry
15 is cleared by Internal Power On Reset.
Double word-wide bit vector specifying 32 bits in the VLAN filter table.
Description
Description
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