WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 340

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Note:
Note:
10.2.6.11
Note:
Note:
340
Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or an
immediate interrupt (RS=1b, IDE=0b) cancels a pending TIDV interrupt. The TIDV
countdown timer is re-loaded but halted, though it can be re-started by processing a
subsequent transmit descriptor.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00440.
Writing this register with FPD set initiates an immediate expiration of the timer, causing
a write back of any consumed transmit descriptors pending write back, and results in a
transmit timer interrupt in the ICR.
FPD is self clearing.
Transmit Descriptor Control - TXDCTL (0x03828 + n*0x100[n=0..1];
RW)
This register controls the fetching and write back of transmit descriptors. The three
threshold values are used to determine when descriptors are read from and written to
host memory. The values can be in units of cache lines or descriptors (each descriptor
is 16 bytes) based on the GRAN flag.
When GRAN=1b all descriptors are written back (even if not requested).
PTHRESH is used to control when a prefetch of descriptors are considered. This
threshold refers to the number of valid, unprocessed transmit descriptors the chip has
in its on-chip buffer. If this number drops below PTHRESH, the algorithm considers pre-
fetching descriptors from host memory. However, this fetch does not happen unless
there are at least HTHRESH valid descriptors in host memory to fetch.
HTHRESH should be given a non-zero value when ever PTHRESH is used.
PTHRESH
Rsv
HTHRESH
Rsv
WTHRESH
Rsv
GRAN
LWTHRESH
Field
5:0
7:6
13:8
15:14
21:16
23:22
24
31:25
Bit(s)
0x0
0x0
0x0
0x0
0x0
0x0
0b
0x0
Initial
Value
Prefetch Threshold
Reserved
Host Threshold
Reserved
Write-Back Threshold
Reserved
Granularity
Units for the thresholds in this register.
0b = Cache lines
1b = Descriptors
Transmit Descriptor Low Threshold
Interrupt asserted when the number of descriptors pending service in
the transmit descriptor queue (processing distance from the TDT)
drops below this threshold.
82574 GbE Controller—Driver Programing Interface
Description