WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 171

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WG82574L S LBA8

Manufacturer Part Number
WG82574L S LBA8
Description
Manufacturer
Intel
Datasheet

Specifications of WG82574L S LBA8

Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Compliant
Inline Functions—82574 GbE Controller
Figure 36.
7.4.3
The following configuration and parameters are involved:
Cause Mapping in MSI-X Mode
Registers
The interrupt logic consists of the registers listed in the following table, plus the
registers associated with MSI/MSI-X signaling.
Interrupt Cause Registers (ICR)
This register records the interrupts causes to provide to the software information on
the interrupt source.
Interrupt Cause
Interrupt Cause Set
Interrupt Mask Set/Read
Interrupt Mask Clear
Interrupt Auto Clear
Interrupt Auto Mask
• The IVAR.INT_Alloc[4:0] entries map two Tx queues, two Rx queues and other
• The ICR[24:20] bits reflect specific interrupt causes
• Five MSI-X interrupt vectors are provided (calculated based on four vectors for
events to 5 interrupt vectors
queues and one vector for other causes). The requested number of vectors is
loaded from the MSI_X_N fields in the EEPROM into the PCIe MSI-X capability
structure of the function.
Register
ICR
ICS
IMS
IMC
EIAC
IAM
(q u e u e s a n d o t h e r )
In te r r u p t c a u s e s
Acronym
Enables bits in the IMS to be set automatically.
Records all interrupt causes - an interrupt is signaled when
unmasked bits in this register are set.
Enables software to set bits in the Interrupt Cause register.
Sets or reads bits in the interrupt mask.
Clears bits in the Interrupt mask.
Enables bits in the ICR and IMS to be cleared automatically
following MSI-x interrupt without a read or write of the ICR.
4
0
Function
2 0
2 4
3 1
0
IC R
. .
.
V e c t o r
M S I-X
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