MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 871

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.61 Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
22.3.2.62 Port AD0 Data Register 1 (PT1AD0)
Read: Anytime.
Write: Anytime.
This register is associated with AD0 pins PAD[7:0]. These pins can also be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
Freescale Semiconductor
PIFJ[7:4]
PIFJ[2:0]
Reset
Reset
Field
7–0
W
W
R
R
PT1AD07
PIFJ7
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a logic level “1” clears the associated flag.
= Unimplemented or Reserved
PT1AD06
PIFJ6
0
0
6
6
Figure 22-63. Port J Interrupt Flag Register (PIFJ)
Figure 22-64. Port AD0 Data Register 1 (PT1AD0)
PT1AD05
Table 22-57. PIEJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PIFJ5
0
0
5
5
PT1AD04
PIFJ4
0
0
4
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
PT1AD03
0
0
0
3
3
PT1AD02
PIFJ2
0
0
2
2
PT1AD01
PIFJ1
0
0
1
1
PT1AD00
PIFJ0
0
0
0
0
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