MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 501

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

11.4.5.5
This module allows to check for collisions on the LIN bus.
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
Freescale Semiconductor
Output Transmit
•
•
•
•
•
Input Receive
Bit Error
Shift Register
Shift Register
The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
The transmission is aborted and the byte in transmit buffer is discarded.
the transmit data register empty and the transmission complete flag will be set
The bit error interrupt flag, BERRIF, will be set.
No further transmissions will take place until the BERRIF is cleared.
LIN Transmit Collision Detection
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
Receive Shift
Register
Transmit Shift
Register
Compare
Sample
Point
0
1
2
Figure 11-19. Timing Diagram Bit Error Detection
3
Synchronizer Stage
Figure 11-18. Collision Detect Principle
4
MC9S12XDP512 Data Sheet, Rev. 2.21
BERRM[1:0] = 0:1
5
Bus Clock
6
7
Compare Sample Points
NOTE
8
9
RXD Pin
TXD Pin
10
11
Chapter 11 Serial Communication Interface (S12SCIV5)
BERRM[1:0] = 1:1
12
13
14
LIN Physical Interface
15
0
LIN Bus
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