MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 870

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.59 Port J Polarity Select Register (PPSJ)
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
22.3.2.60 Port J Interrupt Enable Register (PIEJ)
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port J.
872
PPSJ[7:4]
PPSJ[2:0]
PIEJ[7:4]
PIEJ[2:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PPSJ7
PIEJ7
Polarity Select Port J
0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register.
1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register.
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
0
0
7
7
A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as general purpose input or as IIC port.
A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as input.
= Unimplemented or Reserved
= Unimplemented or Reserved
PPSJ6
PIEJ6
0
0
6
6
Figure 22-62. Port J Interrupt Enable Register (PIEJ)
Figure 22-61. Port J Polarity Select Register (PPSJ)
Table 22-55. PPSJ Field Descriptions
Table 22-56. PIEJ Field Descriptions
PPSJ5
MC9S12XDP512 Data Sheet, Rev. 2.21
PIEJ5
0
0
5
5
PPSJ4
PIEJ4
0
0
4
4
Description
Description
0
0
0
0
3
3
PPSJ2
PIEJ2
0
0
2
2
Freescale Semiconductor
PPSJ1
PIEJ1
0
0
1
1
PPSJ0
PIEJ0
0
0
0
0