MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 719

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.4.4.1
On entering final state a trigger may be issued to the trace buffer according to the trace position control as
defined by the TALIGN field (see
TSOURCE bits in the trace control register DBGTCR are cleared then the trace buffer is disabled and the
transition to final state can only generate a breakpoint request. In this case or upon completion of a tracing
session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to
the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session.
19.4.5
The trace buffer is a 64 lines deep by 64-bits wide RAM array. The DBG module stores trace information
in the RAM array in a circular buffer format. The CPU accesses the RAM array through a register window
(DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace buffer line is
read via the CPU, an internal pointer into the RAM is incremented so that the next read will receive fresh
information. Data is stored in the format shown in
DBGCNT[6:0] are incremented. Tracing of CPU activity is disabled when the BDM is active but tracing
of XGATE activity is still possible. Reading the trace buffer while the BDM is active returns invalid data
and the trace buffer pointer is not incremented.
19.4.5.1
Using the TALIGN bits (see
to align the trigger with the end, the middle or the beginning of a tracing session.
If end or mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered.
The transition to final state if end is selected signals the end of the tracing session. The transition to final
state if mid is selected signals that another 32 lines will be traced before ending the tracing session. Tracing
with begin-trigger starts at the opcode of the trigger.
19.4.5.1.1
Storing with begin-trigger, data is not stored in the trace buffer until the final state is entered. Once the
trigger condition is met the DBG module will remain armed until 64 lines are stored in the trace buffer. If
the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger
will be stored in the trace buffer. Using begin-trigger together with tagging, if the tagged instruction is
about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
19.4.5.1.2
Storing with mid-trigger, data is stored in the trace buffer as soon as the DBG module is armed. When the
trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of
the number of lines stored before the trigger occurred, then the DBG module is disarmed and no more data
is stored. If the trigger is at the address of a change of flow instruction the trigger event is not stored in the
trace buffer. Using mid-trigger with tagging, if the tagged instruction is about to be executed then the trace
Freescale Semiconductor
Trace Buffer Operation
Final State
Trace Trigger Alignment
Storing with Begin-Trigger
Storing with Mid-Trigger
Section 19.3.1.3, “Debug Trace Control Register
Section 19.3.1.3, “Debug Trace Control Register
MC9S12XDP512 Data Sheet, Rev. 2.21
Table
19-39. After each store the counter register bits
Chapter 19 S12X Debug (S12XDBGV2) Module
(DBGTCR)”) it is possible
(DBGTCR)”). If the
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