MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 153

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

4.4.1.2
The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold
machine.
4.4.1.3
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly
charged to the sample potential.
4.4.1.4
The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8
or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the
stored analog sample potential with a series of digitally generated analog potentials. By following a binary
search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled
potential.
When not converting the A/D machine disables its own clocks. The analog electronics continue drawing
quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog
power consumption.
Only analog input signals within the potential range of V
in a non-railed digital output codes.
4.4.2
This subsection explains some of the digital features in more detail. See register descriptions for all details.
4.4.2.1
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to
be edge or level sensitive with polarity control.
combinations of control bits and their effect on the external trigger function.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
Freescale Semiconductor
ETRIGLE
X
X
0
0
1
1
Digital Sub-Block
ETRIGP
Analog Input Multiplexer
Sample Buffer Amplifier
Analog-to-Digital (A/D) Machine
External Trigger Input
X
X
0
1
0
1
ETRIGE
0
0
1
1
1
1
SCAN
Table 4-27. External Trigger Control Bits
X
X
X
X
0
1
MC9S12XDP512 Data Sheet, Rev. 2.21
Ignores external trigger. Performs one conversion sequence and stops.
Ignores external trigger. Performs continuous conversion sequences.
Falling edge triggered. Performs one conversion sequence per trigger.
Rising edge triggered. Performs one conversion sequence per trigger.
Trigger active low. Performs continuous conversions while trigger is active.
Trigger active high. Performs continuous conversions while trigger is active.
Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
Table 4-27
RL
gives a brief description of the different
to V
RH
Description
(A/D reference potentials) will result
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