MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 176

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.8
Read: Anytime, returns unpredictable values
Write: Anytime in special modes, unimplemented in normal modes
5.3.2.9
This register contains the SC bit used to enable special channel conversions.
Read: Anytime, returns unpredictable values for Bit7 and Bit6
Write: Anytime
176
Reset
Reset
Field
SC
0
W
W
R
R
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC,
CB and CA of ATDCTL5.
0 Special channel conversions disabled
1 Special channel conversions enabled
Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result
Reserved Register (ATDTEST0)
ATD Test Register 1 (ATDTEST1)
U
U
1
0
7
7
Writing to this register when in special modes can alter functionality.
SC
1
1
1
1
1
in unpredictable ATD behavior.
= Unimplemented or Reserved
= Unimplemented or Reserved
U
U
0
0
6
6
CC
Figure 5-11. ATD Test Register 1 (ATDTEST1)
Figure 5-10. Reserved Register (ATDTEST0)
0
1
1
1
1
Table 5-19. Special Channel Select Coding
Table 5-18. ATDTEST1 Field Descriptions
Table 5-19
MC9S12XDP512 Data Sheet, Rev. 2.21
U
0
0
0
5
5
lists the coding.
CB
X
0
0
1
1
NOTE
U
0
0
0
4
4
Description
CA
X
0
1
0
1
U
0
0
0
3
3
Analog Input Channel
(V
U
0
0
0
2
2
Reserved
Reserved
RH
+V
V
V
RH
RL
RL
) / 2
Freescale Semiconductor
U
0
0
0
1
1
SC
U
0
0
0
0