MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 133

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Read: Anytime
Write: Anytime
Freescale Semiconductor
ETRIGLE
Reset
ETRIGP
ETRIGE
ASCIE
ASCIF
ADPU
AFFC
AWAI
Field
W
7
6
5
4
3
2
1
0
R
ADPU
0
7
ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will
ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the
ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down,
the ATD requires a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during Wait mode
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 4-7
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
details.
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of
the ETRIG[3:0] inputs as described in
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Interrupt will be requested whenever ASCIF = 1 is set.
ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see
Section 4.3.2.7, “ATD Status Register 0
0 No ATD interrupt occurred
1 ATD sequence complete interrupt pending
to clear the associate CCF flag).
cause the associate CCF flag to clear automatically.
After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of
this conversion should be ignored.
= Unimplemented or Reserved
for details.
AFFC
0
6
Figure 4-5. ATD Control Register 2 (ATDCTL2)
Table 4-6. ATDCTL2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
AWAI
0
5
Table
ETRIGLE
(ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
0
4
4-5. If external trigger source is one of the AD channels, the digital
Description
ETRIGP
0
3
ETRIGE
0
2
ASCIE
0
1
Table 4-7
ASCIF
for
0
0
133