MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 1227
MC9S12XDP512CAL
Manufacturer Part Number
MC9S12XDP512CAL
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512CAL.pdf
(1348 pages)
Specifications of MC9S12XDP512CAL
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
91
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(16-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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29.6.2
The MCU can be unsecured in special single chip mode by erasing the Flash module by the following
method:
After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special
single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the
UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security
state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte
may be programmed to the unsecure state by the following method:
29.7
29.7.1
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash memory according to
29.7.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
29.8
The Flash module can generate an interrupt when all Flash command operations have completed, when the
Flash address, data and command buffers are empty.
Freescale Semiconductor
Flash Address, Data and Command Buffers empty
All Flash commands completed
•
•
•
•
•
Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM
secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass
erase command write sequence to erase the Flash memory.
Send BDM commands to execute a word program sequence to program the Flash security byte to
the unsecured state and reset the MCU.
FPROT — Flash Protection Register (see
FCTL - Flash Control Register (see
FSEC — Flash Security Register (see
Resets
Interrupts
Unsecuring the MCU in Special Single Chip Mode using BDM
Flash Reset Sequence
Reset While Flash Command Active
Interrupt Source
Table 29-19. Flash Interrupt Sources
MC9S12XDP512 Data Sheet, Rev. 2.21
Section
Section
Table
Section
(FSTAT register)
(FSTAT register)
Interrupt Flag
29.3.2.8).
29-1:
29.3.2.2).
CBEIF
CCIF
29.3.2.5).
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
(FCNFG register)
(FCNFG register)
Local Enable
CBEIE
CCIE
Global (CCR) Mask
I Bit
I Bit
1229
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