MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 571

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

15.1.2.3
The BDM can be used until all bus masters (e.g., CPU or XGATE) are in stop mode. When CPU is in a
low power mode (wait or stop mode) all BDM firmware commands as well as the hardware
BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter
BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter
a low power mode during BDM active mode.
If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled
and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft
reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM
is now ready to receive a new command.
15.1.3
A block diagram of the BDM is shown in
Freescale Semiconductor
System
Host
Block Diagram
Low-Power Modes
Register Block
BKGD
BDMSTS
Register
BDMACT
ENBDM
CLKSW
UNSEC
TRACE
SDV
Interface
Serial
MC9S12XDP512 Data Sheet, Rev. 2.21
Control
Figure 15-1. BDM Block Diagram
Data
Figure
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
15-1.
Execution
and
Chapter 15 Background Debug Module (S12XBDMV2)
Bus Interface
Control Logic
and
Address
Data
Control
Clocks
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