MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 52

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 1 Device Overview MC9S12XD-Family
1.2.2
Table 1-7
of the S12XD, S12XB and S12XA family please refer to
52
Function 1
PAD[23:08]
PAD[07:00]
VREGEN
RESET
PB[7:0]
PB[7:1]
PC[7:0]
PD[7:0]
PA[7:0]
PA[7:0]
EXTAL
BKGD
Name
TEST
XTAL
XFC
PB0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
Pin
summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts
ADDR[15:8] IVD[15:8]
Function 2
DATA[15:8]
ADDR[7:1]
DATA[7:0]
Signal Properties Summary
AN[23:8]
ECLKX2
AN[7:0]
ADDR0
LSTRB
MODC
TAGHI
Name
ECLK
R/W
IRQ
Pin
RE
—
—
—
—
—
—
—
—
Function 3
IVD[7:0]
XCLKS
MODB
MODA
Name
UDS
LDS
Pin
WE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 1-7. Signal Properties Summary (Sheet 1 of 4)
Function 4
EROMCTL
TAGLO
Name
MC9S12XDP512 Data Sheet, Rev. 2.21
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function 5
Name
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Supply
V
V
V
Power
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDPLL
DDPLL
N.A.
DDPLL
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDX
DDX
DDA
DDA
Appendix E Derivative
RESET pin
Always on
PUCR
PER0/
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
CTRL
PER1
PER1
pin is low: down
pin is low: down
While RESET
While RESET
Internal Pull
NA
NA
NA
Resistor
PULLUP
Disabled Port AD I/O, Port AD inputs
Disabled Port AD I/O, Port AD inputs
Disabled Port A I/O
Disabled Port BI/O
Disabled Port A I/O, address bus,
Disabled Port B I/O, address bus,
Disabled Port B I/O, address bus,
Disabled Port C I/O, data bus
Disabled Port D I/O, data bus
DOWN Test input
Reset
State
NA
NA
NA
Up
Up
Up
Up
Up
Up
Up
Differences.
Oscillator pins
External reset
Voltage regulator enable
Input
PLL loop filter
Background debug
of ATD1 and
analog inputs of ATD1
of ATD0 and
analog inputs of ATD0
internal visibility data
internal visibility data
upper data strobe
Port E I/O, system clock
output, clock select
Port E I/O, tag high, mode
input
Port E I/O, read enable,
mode input, tag low input
Port E I/O, bus clock output
Port E I/O, low byte data
strobe, EROMON control
Port E I/O, read/write
Port E Input, maskable
interrupt
Freescale Semiconductor
Description