MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 849

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.32 Port M Data Direction Register (DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN[3:0], TXD3). TheyAlso forces the I/O state to be an input for each port line associated with an
enabled input (RXCAN[3:0], RXD3). In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
Freescale Semiconductor
DDRM[7:0]
Reset
Field
7–0
W
R
DDRM7
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTM or PTIM registers, when changing the DDRM register.
DDRM6
0
6
Figure 22-34. Port M Data Direction Register (DDRM)
Table 22-33. DDRM Field Descriptions
DDRM5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRM4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRM3
0
3
DDRM2
0
2
DDRM1
0
1
DDRM0
0
0
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