PIC16F707-E/P Microchip Technology, PIC16F707-E/P Datasheet - Page 39

• Manufacturer Part Number: PIC16F707-E/P
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.0
The PIC16F707/PIC16LF707 device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act accordingly. Some interrupts can be configured
to wake the MCU from Sleep mode.
The PIC16F707 family has 16 interrupt sources,
differentiated by corresponding interrupt enable and
flag bits:
• Timer0 Overflow Interrupt
• External Edge Detect on INT Pin Interrupt
• PORTB Change Interrupt
• Timer1 Gate Interrupt
• A/D Conversion Complete Interrupt
FIGURE 4-1:
 2010 Microchip Technology Inc.
IOC-RB0
IOC-RB1
IOC-RB2
IOC-RB3
IOC-RB4
IOC-RB5
IOC-RB6
IOC-RB7
IOCB0
IOCB1
IOCB2
IOCB3
IOCB4
IOCB5
IOCB6
IOCB7
INTERRUPTS
INTERRUPT LOGIC
TMR1GIE
TMR1GIF
TMR3GIF
TMR3GIE
TMR2IE
TMR1IF
TMR1IE
TMRBIF
TMRBIE
TMR2IF
CCP1IF
CCP1IE
CCP2IF
CCP2IE
TMRAIF
TMRAIE
TMR3IF
TMR3IE
SSPIF
SSPIE
RCIE
RCIF
ADIF
ADIE
TXIF
TXIE
Preliminary
PIC16F707/PIC16LF707
• AUSART Receive Interrupt
• AUSART Transmit Interrupt
• SSP Event Interrupt
• CCP1 Event Interrupt
• Timer2 Match with PR2 Interrupt
• Timer1 Overflow Interrupt
• CCP2 Event Interrupt
• TimerA Overflow Interrupt
• TimerB Overflow Interrupt
• Timer3 Overflow Interrupt
• Timer3 Gate Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
Note 1:
TMR0IF
TMR0IE
RBIE
INTF
INTE
RBIF
PEIE
GIE
Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 21.1
“Wake-up from Sleep”.
Wake-up (If in Sleep mode)
Interrupt to CPU
DS41418A-page 39
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