PIC16F707-E/P Microchip Technology, PIC16F707-E/P Datasheet - Page 21

• Manufacturer Part Number: PIC16F707-E/P
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 2-2:
 2010 Microchip Technology Inc.
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
Legend:
Note 1:
Address
Bank 2
( 2)
( 2)
( 2)
( 2)
( 1),(2)
( 2)
2:
3:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
INDF
TMR0
PCL
STATUS
FSR
TACON
CPSBCON0
CPSBCON1
CPSACON0
CPSACON1
PCLATH
INTCON
PMDATL
PMADRL
PMDATH
PMADRH
TMRA
TBCON
TMRB
DACCON0
DACCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
TMRAON
TMRBON
CPSBON
CPSAON
DACEN
Bit 7
GIE
IRP
Addressing this location uses contents of FSR to address data memory (not a physical register)
—
—
—
—
—
—
CPSBRM
CPSARM
DACLPS
PEIE
Bit 6
RP1
—
—
—
—
—
—
—
—
Program Memory Read Address Register Low Byte
TMR0IE
DACOE
TBCS
TACS
Program Memory Read Data Register Low Byte
Bit 5
RP0
Program Counter’s (PC) Least Significant Byte
—
—
—
—
—
—
—
Indirect Data Memory Address Pointer
Preliminary
Write Buffer for the upper 5 bits of the Program Counter
DACR4
TimerA Module Register
TimerB Module Register
Timer0 Module Register
TASE
Program Memory Read Data Register High Byte
TBSE
Bit 4
INTE
TO
—
—
—
—
—
PIC16F707/PIC16LF707
Program Memory Read Address Register High Byte
CPSBRNG1 CPSBRNG0 CPSBOUT
CPSARNG1 CPSARNG0 CPSAOUT
CPSBCH3
CPSACH3
DACPSS1
TBPSA
DACR3
TAPSA
RBIE
Bit 3
PD
CPSBCH2
CPSACH2
DACPSS0
TMR0IF
DACR2
TAPS2
TBPS2
Bit 2
Z
CPSBCH1 CPSBCH0
CPSACH1 CPSACH0
DACR1
TAPS1
TBPS1
Bit 1
INTF
DC
—
DACR0
TBXCS
TAXCS
TAPS0
TBPS0
Bit 0
RBIF
—
C
DS41418A-page 21
xxxx xxxx
0000 0000
0000 0000
0001 1xxx
xxxx xxxx
0-00 0000
00-- 0000
---- 0000
0--- 0000
---- 0000
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---x xxxx
0000 0000
0-00 0000
0000 0000
000- 00--
---0 0000
POR, BOR
Value on:
Value on all
xxxx xxxx
0000 0000
0000 0000
000q quuu
uuuu uuuu
0-00 0000
00-- 0000
---- 0000
0--- 0000
---- 0000
---0 0000
0000 000u
uuuu uuuu
uuuu uuuu
--uu uuuu
---u uuuu
0000 0000
0-00 0000
0000 0000
000- 00--
---0 0000
resets
other