PIC16F707-E/P Microchip Technology, PIC16F707-E/P Datasheet - Page 184

• Manufacturer Part Number: PIC16F707-E/P
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F707/PIC16LF707
21.1.1
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
FIGURE 21-1:
TABLE 21-1:
DS41418A-page 184
INTCON
IOCBF
PIE1
PIE2
PIR1
PIR2
STATUS
Legend:
Instruction Flow
Name
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
(INTCON reg.)
Note
Interrupt flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
cleared.
OSC1
1:
2:
3:
4:
PC
TMR1GIE
TMR3GIE
TMR1GIF
TMR3GIF
(1)
IOCBF7
(2)
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
WAKE-UP USING INTERRUPTS
Bit 7
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
T
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
GIE
IRP
OST
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
IOCBF6
TMR3IE
TMR3IF
WAKE-UP FROM SLEEP THROUGH INTERRUPT
PEIE
ADIE
ADIF
Bit 6
RP1
OSC
(drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
Inst(PC + 1)
Sleep
TMRBIE
PC + 1
TMR0IE
IOCBF5
TMRBIF
RCIE
RCIF
Bit 5
RP0
TMRAIE
TMRAIF
IOCBF4
Processor in
INTE
Bit 4
TXIE
TXIF
TO
Sleep
PC + 2
Preliminary
IOCBF3
SSPIE
SSPIF
T
IOCIE
Bit 3
OST (3)
PD
—
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
TMR0IF
IOCBF2
CCP1IE
CCP1IF
Inst(PC + 2)
Inst(PC + 1)
Bit 2
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
—
—
PC + 2
Z
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
cuted
TMR2IE
IOCBF1
TMR2IF
Bit 1
INTF
DC
—
—
(4)
Dummy Cycle
PC + 2
IOCBF0
TMR1IE
CCP2IE
TMR1IF
CCP2IF
IOCIF
Bit 0
C
 2010 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
0000 000x
0000 0000
0000 0000
0000 ---0
0000 0000
0000 ---0
0001 1xxx
POR, BOR
Value on
Inst(0005h)
Inst(0004h)
0005h
Value on all
0000 000x
0000 0000
0000 0000
0000 ---0
0000 0000
0000 ---0
000q quuu
Resets
other