PIC16F707-E/P Microchip Technology, PIC16F707-E/P Datasheet - Page 23

• Manufacturer Part Number: PIC16F707-E/P
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.2.1
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
IRP
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
STATUS Register
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
R/W-0
RP1
STATUS: STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
RP0
(1)
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
R-1
TO
Preliminary
PIC16F707/PIC16LF707
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 23.0
“Instruction Set Summary”).
R-1
PD
Note 1: The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
R/W-x
Z
(1)
x = Bit is unknown
R/W-x
(1)
DC
(1)
DS41418A-page 23
R/W-x
C
(1)
bit 0