PIC16F707-E/P Microchip Technology, PIC16F707-E/P Datasheet - Page 103

• Manufacturer Part Number: PIC16F707-E/P
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 13-5:
13.6.3
The TxG pin is one source for Timer1/3 gate control.
It can be used to supply an external source to the
Timer1/3 gate circuitry. Timer1 gate can be configured
for the T1G pin and Timer3 gate can be configured for
the T3G pin.
13.6.4
When TimerA/B increments from FFh to 00h a low-to-
high pulse will automatically be generated and
internally supplied to the Timer1/3 gate circuitry. Timer1
gate can be configured for TimerA overflow and Timer3
gate can be configured for TimerB overflow.
13.6.5
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timer1/3 gate cir-
cuitry. Both Timer1 gate and Timer3 gate can be
configured for the Timer2 match.
TABLE 13-6:
 2010 Microchip Technology Inc.
TxGSS
WDTE
00
01
10
11
1
1
0
0
TIMERA/B OVERFLOW GATE
TIMER2 MATCH GATE OPERATION
TxG PIN GATE OPERATION
OPERATION
Timer1 Gate Pin
Overflow of TimerA
(TMRA increments from FFh to 00h)
Timer2 match PR2
(TMR2 increments to match PR2)
Count Enabled by WDT Overflow
(Watchdog Time-out interval expired)
TMRxGE = 1 and
TIMER1/3 GATE SOURCES
WDT/TIMER1/3 GATE INTERRACTION
TxGSS = 11
N
N
Y
Y
Timer1 Gate Source
WDT Oscillator
Enable
Y
Y
Y
N
Preliminary
PIC16F707/PIC16LF707
Timer3 Gate Pin
Overflow of TimerB
(TMRB increments from FFh to 00h)
Timer2 match PR2
(TMR2 increments to match PR2)
Count Enabled by WDT Overflow
(Watchdog Time-out interval expired)
WDT Reset
13.6.6
The Watchdog Timer oscillator, prescaler and counter
will be automatically turned on when TMRxGE = 1 and
TxGSS selects the WDT as a gate source for Timer1/3
(TxGSS = 11). TMRxON does not factor into the oscil-
lator, prescaler and counter enable. See Table 13-6.
Both Timer1 gate and Timer3 gate can be configured
for Watchdog overflow.
The PSA and PS bits of the OPTION register still
control what time-out interval is selected. Changing the
prescaler during operation may result in a spurious
capture.
Enabling the Watchdog Timer oscillator does not
automatically enable a Watchdog Reset or wake-up
from Sleep upon counter overflow.
As the gate signal coming from the WDT counter will
generate different pulse widths, depending on if the
WDT is enabled, when the CLRWDT instruction is exe-
cuted, and so on, Toggle mode must be used. A spe-
cific sequence is required to put the device into the
correct state to capture the next WDT counter interval.
Note:
Y
Y
N
N
WATCHDOG OVERFLOW GATE
OPERATION
When using the WDT as a gate source for
Timer1/3,
Watchdog
instructions) will affect the time interval
being measured for capacitive sensing.
This includes waking from Sleep. All other
interrupts that might wake the device from
Sleep should be disabled to prevent them
from disturbing the measurement period.
Timer3 Gate Source
Wake-up
Y
Y
N
N
operations
Timer
(CLRWDT,
WDT Available for
DS41418A-page 103
that
TxG Source
clear
N
Y
Y
N
SLEEP
the