PIC16F707-E/P Microchip Technology, PIC16F707-E/P Datasheet - Page 112

• Manufacturer Part Number: PIC16F707-E/P
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F707/PIC16LF707
14.1
The TimerA/B modules can be used as either 8-bit tim-
ers or 8-bit counters. Additionally, the modules can also
be used to set Timer1’s/Timer3’s period of measure-
ment for the capacitive sensing modules via Timer1’s
or Timer3’s gate feature.
TABLE 14-1:
14.1.1
The TimerA/B modules will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMRxCS bit of the TxCON
registers.
When TMRx is written, the increment is inhibited for
two instruction cycles immediately following the write.
14.1.2
In 8-bit Counter mode, the TimerA/B modules will
increment on every rising or falling edge of the TxCKI
pin or the Capacitive Sensing Oscillator (CPSxOSC)
signal. 8-bit Counter mode using the TxCKI pin is
selected by setting the TMRxCS bit of the TxCON
register to ‘1’ and resetting the TxXCS bit in the
CPSxCON0 register to ‘0’. 8-bit Counter mode using the
Capacitive Sensing Oscillator (CPSxOSC) signal is
selected by setting the TMRxCS bit in the TxCON
register to ‘1’ and setting the TxXCS bit in the
CPSxCON0 register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMRxSE bit
in the TxCON register.
DS41418A-page 112
Note:
Cap Sense
Oscillator
CPS A
CPS B
TimerA/B Operation
8-BIT TIMER MODE
The value written to the TMRx register can
be adjusted, in order to account for the two
instruction cycle delay when TMRx is
written.
8-BIT COUNTER MODE
CPSOSC/TIMER
ASSOCIATION
Divider
TimerA
TimerB
Timer
Measurement
Period
Timer1
Timer3
Preliminary
14.1.3
For TimerA/B modules, the software programmable
prescaler is exclusive to the Timer. The prescaler is
enabled by clearing the TMRxPSA bit of the TxCON
register.
There are 8 prescaler options for TimerA/B modules
ranging from 1:2 to 1:256. The prescale values are
selectable via the TMRxPS<2:0> bits of the TxCON
register for TimerA/B. In order to have a 1:1 prescaler
value for the TimerA/B modules, the prescaler must be
disabled.
The prescaler is not readable or writable. When the
prescaler is enabled or assigned to the Timer module, all
instructions writing to the TMRx register will clear the
prescaler. Enabling the TimerA/B modules also clears
the prescaler.
14.1.4
TimerA/B will generate an interrupt when the
corresponding TMR register overflows from FFh to
00h. The TMRxIF interrupt flag bit of the PIR2 register
is set every time the TMRx register overflows. These
interrupt flag bits are set regardless of whether or not
the relative Timer interrupt is enabled. The interrupt
flag bits can only be cleared in software. The TimerA/B
interrupt enable bits are the TMRxIE in the PIE2
register.
14.1.5
When
synchronization of the TxCKI input and the TMRx
register is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase
clocks. Therefore, the high and low periods of the
external
requirements as shown in Section 25.0 “Electrical
Specifications”.
14.1.6
Operation of TimerA/B is enabled by setting the
TMRxON bit of the TxCON register. When the module
is disabled, the value in the TMRx register is
maintained. Enabling the TMRx module will reset the
prescaler used by the counter.
14.1.7
TimerA and TimerB cannot operate while the processor
is in Sleep mode. The contents of the TMRx registers
will remain unchanged while the processor is in Sleep
mode.
Note:
TimerA/B
clock
SOFTWARE PROGRAMMABLE
PRESCALER
TIMERA/B INTERRUPT
TimerA/B interrupts cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
USING TIMERA/B WITH AN
EXTERNAL CLOCK
TIMER ENABLE
OPERATION DURING SLEEP
source
is
 2010 Microchip Technology Inc.
in
must
Counter
meet
mode,
the
timing
the