DJLXT384LE Intel, DJLXT384LE Datasheet - Page 89

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

9.4
9.4.1
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 51. Boundary Scan Register (BSR) (Sheet 1 of 4)
JTAG Register Description
The following paragraphs describe each of the registers represented in
Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply
and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register.
Bidirectional pins or tristate pins require more than one position in the register.
BSR scan cells and their functions. Data into the BSR is shifted in LSB first.
The Analog Test Port can be used to verify continuity across the coupling transformer’s primary
winding as shown in
appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface.
Bit #
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
RPOS1
LOOP0
LOOP0
LOOP1
LOOP1
LOOP2
LOOP2
LOOP3
LOOP3
LOOP4
LOOP4
LOOP5
LOOP5
LOOP6
LOOP6
LOOP7
LOOP7
TPOS1
TNEG1
RCLK1
TCLK1
Signal
Pin
N/A
I/O Type
Figure
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
-
I
I
I
17. By applying a stimulus to the AT1 input, a known voltage will
PDOENB
Symbol
RPOS1
PADD0
PADD1
PADD2
PADD3
PADD4
PADD5
PADD6
PADD7
TPOS1
TNEG1
TCLK1
RCLK1
PDO0
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
Bit
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
PDOENB controls the LOOP0 through LOOP7 pins.
Setting PDOENB to “0” configures the pins as outputs. The
output value to the pin is set in PDO[0...7].
Setting PDOENB to “1” tristates all the pins. The input value
to the pins can be read in PADD[0...7].
Comments
Figure
15.
Table 51
shows the
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