DJLXT384LE Intel, DJLXT384LE Datasheet - Page 77
DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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8.2
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 27. Register Addresses for Serial and Parallel Interfaces
Register Addresses
Table 27
ID
Analog Loopback
Remote Loopback
TAOS Enable
LOS Status Monitor
LOS Interrupt Enable
LOS Interrupt Status
Reset
Performance Monitoring
Digital Loopback
LOS/AIS Criteria Selection
Automatic TAOS Select
Global Control
Output Enable
AIS Status Monitor
AIS Interrupt Enable
AIS Interrupt Status
•
•
Pins A7:1 (used for the LXT384 Transceiver Host Processor mode with a serial interface)
Pins A7:0 (used for the LXT384 Transceiver Host Processor mode with a parallel interface)
Register Name
lists the register names and register addresses on:
(Address from Pins A7:1)
Intel
Host Processor Mode Registers Addresses
Serial Interface
xx00000
xx00001
xx00010
xx00100
xx01000
xx01010
xx10010
xx10100
xx10101
xx00011
xx00110
xx01011
xx01100
xx01101
xx01110
xx01111
xx10011
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
(Address from Pins A7:0)
Parallel Interface
xxx00000
xxx00001
xxx00010
xxx00011
xxx00100
xxx00110
xxx01000
xxx01010
xxx01011
xxx01100
xxx01101
xxx10010
xxx10011
xxx10100
xxx10101
xxx01110
xxx01111
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
77
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