DJLXT384LE Intel, DJLXT384LE Datasheet - Page 78

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
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Table 28. ID Register, ID - 00h
Table 29. Analog Loopback Register, ALOOP - 01h
Table 30. Remote Loopback Register, RLOOP - 02h
Table 31. TAOS Enable Register, TAOS - 03h
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Register Descriptions
Bit
7:0
Bit
7:0
Bit
7:0
Bit
7:0
TAOS7:0
Name
Name
Name
Name
AL7:0
RL7:0
ID7:0
Identification.
The identification register contains a unique revision code that is factory
programmed for each revision of the LXT384 Transceiver.
Analog Loopback.
Setting one of the AL bits to ‘1’ enables analog loopback for its corresponding
transceiver.
Remote Loopback.
Setting one of the RL bits to ‘1’ enables remote loopback for its corresponding
transceiver.
Transmit All Ones (Enable).
NOTE: TAOS is not available in data-recovery mode or the line-driver mode
• Revision code for the LXT384 Transceiver stepping A4 is 00h.
• Revision code for the LXT384 Transceiver stepping A5 is 15h.
• On power-up, the TAOS7:0 bits are cleared to ‘0’.
• Setting one of the TAOS bits to ‘1’ causes a continuous stream of marks
• There are two possible timing references for these bits, depending on the
(that is, ones) to be sent out to the TTIP pin and TRING pin of the
corresponding transmitter.
availability of MCLK. If MCLK:
• Is not available, then the channel TCLK is used as the timing reference
• Is available, MCLK is used as the timing reference for the output.
for the output.
(that is, when both MCLK = High and TCLK = High).
Description
Description
Description
Description
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
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