DJLXT384LE Intel, DJLXT384LE Datasheet - Page 121
DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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11.3
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 71. Serial I/O Timing Characteristics
Figure 29. Serial Input Timing
SCLK
SCLK
SDI
SDI
CS
CS
Host Processor Mode - Serial Interface Timing
Table 71
a serial interface.
Figure 29
Rise/fall time any pin
SDI to SCLK setup time
SCLK to SDI hold time
SCLK low time
SCLK high time
SCLK rise and fall time
CS falling edge to SCLK rising edge
Last SCLK edge to CS rising edge
CS inactive time
SCLK to SDO valid delay time
SCLK falling edge or CS rising edge to SDO high
impedance
1. Typical figures are at 25 C° and are for design aid only, not guaranteed, and not subject to production
testing.
t
t
t
t
DC
DC
CC
CC
LSB
LSB
lists serial I/O timing for a Motorola or Intel
is a timing diagram for serial input to the Host Processor interface.
t
t
CH
CH
CONTROL BYTE
CONTROL BYTE
t
t
CL
CL
Parameter
t
t
CDH
CDH
Intel
LSB
LSB
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
®
Sym.
Tr, Tf
Tcwh
Tcdh
Tcch
Tcdv
Tcdz
Tdc
Tch
Tcc
Tcl
Trf
DATA BYTE
DATA BYTE
processor in the Host Processor mode with
t
t
CDH
CDH
Min.
25
25
10
10
50
5
5
Typ.
10
1
MSB
MSB
Max.
100
50
5
t
t
CCH
CCH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
CWH
CWH
C
mA, 50 pF
Condition
Load
Test
= 1.6
121
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