DJLXT384LE Intel, DJLXT384LE Datasheet - Page 61

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
When the LXT384 Transceiver is in the:
For information on jitter attenuation as it applies specifically to the receiver, see
Attenuation”.
Standard E1 jitter-attenuation recommendations and specifications that the LXT384 Transceiver
JA meets are the following. (For more recommendations and specifications, see
“Recommendations and
The LXT 384 Transceiver also supports the following T1 jitter attenuation specifications:
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Host Processor mode:
Hardware mode:
European Telecommunications Standards Institute (ETSI) publication, ETSI CTR12/13
International Telecommunication Union (ITU) publications:
BAPT220
AT&T Pub 62411
GR-25-CORE, Category I, R5-203
TR-TSY-000009
— The Global Control Register (GCR,
— Depending on the GCR register FIFO64 bit setting, the depth of the FIFO used in the JA is
— The low-limit jitter attenuator corner frequency depends on the FIFO depth and the JACF
— The JASEL pin determines whether JA is positioned in the receive or transmit path.
— The FIFO length is fixed to 64 bits.
— The low-limit jitter attenuator corner frequency is fixed to 3.5 Hz for E1 mode, or 6 Hz for
— ITU-T G.736
— ITU-T G.742, when used with the SXT6234 E2-E1 mux/demux.
— ITU-T G.783, combined jitter when used with the SXT6251 21E1 mapper.
positioned in the receive or transmit path.
either a 32 x 2-bit FIFO or a 64 x 2-bit FIFO. (For FIFO64 bit details, see
Chapter 8.0,
bit setting in the GCR register. (For JACF bit details, see
“Registers”.)
T1 mode. (For more information on the JA corner frequency, see
14.0, “Jitter
Performance”.)
“Registers”.)
Specifications”.)
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table
43) JASEL bits determine whether the JA is
Table 43
Table 76
in
Chapter 8.0,
Section 6.6, “Jitter
Chapter 15.0,
Table 43
in
Chapter
in
61