DJLXT384LE Intel, DJLXT384LE Datasheet - Page 50

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
6.3.4
6.3.5
6.3.6
50
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
6.3.5.1
6.3.5.2
Receiver Data Recovery Mode
In data-recovery mode, the combined analog/digital LOS detector circuit uses only its LOS analog
part, which complies with the ITU-G.775 recommendation. The LOS digital timing is derived from
an internal self-timed circuit. RPOS/RNEG stay active during the loss of signal.
The LXT384 Transceiver monitors the incoming signal amplitude. Typically, any signal below
200mV for more than 30μs asserts the corresponding LOS pin. The LOS condition clears when the
signal amplitude rises above 250mV. To declare an LOS condition in accordance to ITU G.775, the
LXT384 Transceiver requires periods that are more than 10 bits and less than 255 bits.
Receiver Alarm Indication Signal (AIS) Detection
The receiver performs an Alarm Indication Signal (AIS) detection independently of any loopback
mode. This feature is available only in the Host Processor mode and only in the clock-recovery
mode.
Because there is no clock in the data-recovery mode, AIS detection does not work in that mode.
AIS requires MCLK to be active, because the AIS function depends on a clock to count the number
of ones in an interval.
After power-on reset, the LACS register
detection mode or the ETSI 3000 233 detection mode, both of which can be used for AIS. For both
ITU G.775 and ETSI ETS 300 233, the AIS condition is:
ANSI T1.231 detection is employed. The AIS condition is:
Receive Alarm Indication Signal (RAIS) Enable
When an LOS condition is detected, enabling or disabling the Receive Alarm Indication Signal
Enable (RAISEN) bit (bit 6) in the Global Control Register (GCR) affects the setting of the AIS
Status Monitor register.
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Declared when in a 512-bit period, the receiver detects less than 3 zeroes in the data stream.
Cleared when in a 512-bit period, the receiver detects 3 or more zeroes in the data stream.
Declared when less than 9 zeros are detected in any string of 8192 bits. This corresponds to a
99.9% ones density over a period of 5.3 ms.
Cleared when the received signal contains 9 or more zeros in any string of 8192 bits.
For details on the RAISEN bit, see
page
For details on the AIS Status Monitor register, see
AIS - 13h” on page
E1 Mode
T1 Mode
83.
85.
Table 43, “Global Control Register, GCR - 0Fh” on
(Table
41) can be set to select either the ITU G.775
Table 47, “AIS Status Monitor Register,
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005