DJLXT384LE Intel, DJLXT384LE Datasheet - Page 29
DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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5.3.3
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 8.
Framer/Mapper Signals - Details
For multi-function pins, the pin name in
Framer/Mapper Receive Signals (Sheet 1 of 2)
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
RDATA7
RDATA6
RDATA5
RDATA4
RDATA3
RDATA2
RDATA1
RDATA0
•
•
1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output.
Table 8
Table 9 on page 31
signals.
Signal
Name
/ RNEG7
/ RNEG6
/ RNEG5
/ RNEG4
/ RNEG3
/ RNEG2
/ RNEG1
/ RNEG0
/ RPOS7
/ RPOS6
/ RPOS5
/ RPOS4
/ RPOS3
/ RPOS2
/ RPOS1
/ RPOS0
lists and describes the LXT384 Transceiver framer/mapper receive signals.
QFP
141
105
143
103
142
104
Pin
112
110
111
69
76
34
41
71
78
32
39
70
77
33
40
4
6
5
lists and describes the LXT384 Transceiver framer/mapper transmit
PBGA
M12
M14
M13
Ball
C12
A12
P12
C14
A14
P14
C13
A13
P13
C3
M3
C1
M1
C2
M2
A3
P3
A1
P1
A2
P2
Intel
Signal
Type
DO
DO
DO
blue bold
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Bipolar Violation Detect Output 7:0.
When unipolar I/O is selected for the LXT384 Transceiver,
BPV acts as an output line code violation detector. If the
LXT384 Transceiver:
For details on Line Code Violations, see
Loss and Line-Code-Violation
For other pin functions, see RNEG.
Receive Clock Output 7:0.
Normally, this pin provides the recovered clock from the
signal received at RTIP and RRING. Under LOS conditions,
MCLK replaces RCLK at the RCLK output. For details, see
Section 6.3.3, “Receiver Loss-Of-Signal
When MCLK is Low:
When MCLK is High:
For details about the relationship between MCLK and
RCLK, see
Signals”, especially
Receive Data Output 7:0.
When unipolar I/O is selected for the LXT384 Transceiver,
RDATA acts as the receive data output.
See
Side” on page
For other pin functions, see RPOS.
• Does not detect an in-service line code violation, BPV
• Detects an in-service line code violation, it asserts BPV
• The LXT384 Transceiver enters the data recovery
• RCLK will be in high impedance state.
• The clock recovery circuit is disabled.
• The RCLK output is then the EX-OR of RPOS and
remains low.
high.
mode.
RNEG. This produces a pseudo-recovered clock.
Section 5.3.1, “Bipolar vs. Unipolar Operation - Receive
print indicates the signal being discussed.
Section 5.5, “Clocks and Clock-Related
27.
Signal Description
Table 11 on page
Signals”.
37.
Section 5.7, “Signal
Detector”.
29
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