DJLXT384LE Intel, DJLXT384LE Datasheet - Page 86

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
9.0
9.1
9.2
86
Figure 15. JTAG Architecture
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
JTAG Boundary Scan
Overview
The LXT384 Transceiver supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan
allows easy access to the interface pins for board testing purposes.
In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT384 Transceiver
also includes analog test port capabilities. This feature provides access to the TIP and RING signals
in each channel (transmit and receive). This way, the signal path integrity across the primary
winding of each coupling transformer can be tested.
Architecture
The basic JTAG architecture of the LXT384 Transceiver is illustrated in
The LXT384 Transceiver JTAG architecture includes a TAP Test Access Port Controller, data
registers and an instruction register. The following paragraphs describe these blocks in detail.
TRST
TMS
TCK
TDI
Controller
TAP
Device Identification Register
Boundry Scan Data Register
Analog Port Scan Register
Instruction Register
Bypass Register
BSR
BYR
ASR
IDR
IR
Revision Date: November 28, 2005
Figure
MUX
Document Number: 248994
15.
Revision Number: 005
TDO