DJLXT384LE Intel, DJLXT384LE Datasheet - Page 65

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

6.8
6.8.1
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Figure 11. TAOS Data Path for Intel
Note: The TAOS mode is inhibited during Remote loopback.
Note:
Transmit All Ones Operations
For Transmit All Ones (TAOS) operations, the LXT384 Transceiver has the following TAOS
modes:
TAOS Generation
When the LXT384 Transceiver is set for a:
Figure 11
•
•
•
•
•
•
•
Section 6.8.1, “TAOS Generation”
Section 6.8.2, “TAOS Generation with Analog Loopback”
Section 6.8.3, “TAOS Generation with Digital Loopback”
Hardware mode, the TAOS mode is set by connecting the TCLK pin high for more than 16
MCLK cycles.
Host Processor mode, the TAOS mode is set by asserting the corresponding bit in the TAOS
register. In case of LOS, Automatic TAOS Select (ATS) insertion can be set with the ATS
register
The TAOS generator uses the clock signal on the MCLK pin as a timing reference. As a result,
when the LXT384 Transceiver is set for data-recovery mode with a Motorola processor, TAOS
does not work because wait states cannot be added. To ensure the output frequency is within
specification limits, MCLK must have the applicable stability.
When TAOS is active, DLOOP does not function.
TPOS
TNEG
TCLK
RPOS
RNEG
MCLK
RCLK
shows how the LXT384 Transceiver generates the Transmit All Ones mode.
(Table
* If Enabled
TAOS mode
42).
®
JA*
LXT384 Transceiver
Intel
Recovery
Timing &
Control
Timing
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
TTIP
TRING
(ALL 1's)
RTIP
RRING
65