DJLXT384LE Intel, DJLXT384LE Datasheet - Page 44

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
5.9
44
Table 16. JTAG Analog Interface Test Signals
Table 17. JTAG Digital Interface Test Signals
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Test Signals
Table 17
input, output, and input/output pins.
The JTAG test signals are compatible with the IEEE 1149.1 boundary-scan test.
AT2
AT1
TCK
TDI
TDO
TMS
TRST
1. AI: Analog Input. AO: Analog Output.
1. DI: Digital Input. DO: Digital Output.
2. See
Signal
Signal
Name
Name
Figure 18, “JTAG Timing” on page
Section 9.4.5, “Instruction Register (IR)” on page
lists and describes the LXT384 Transceiver test signals, which are used to test all digital
QFP
QFP
Pin
Pin
93
94
97
99
98
96
95
PBGA
PBGA
G13
G12
Ball
H13
Ball
F14
F12
F13
F11
Signal
Signal
Type
Type
DO
AO
AI
DI
DI
DI
DI
95.
JTAG Analog Test Port 2:1.
Both test ports are used for test purposes.
See
and
JTAG Test Clock Input.
TCK is the clock input for JTAG.
When TCK is not used, connect it to ground.
JTAG Test Data Input.
TDI, the test data input for JTAG, is used for loading serial
instructions and data into internal test logic. TDI is sampled on the
rising edge of TCK.
TDI is connected high internally and can be left disconnected.
JTAG Test Data Output.
TDO, the test data output for JTAG, is used for reading all serial
configuration and test data from the internal LXT384 Transceiver
test logic. It is updated on the falling edge of TCK.
JTAG Test Mode Select Input.
TMS, used to control the test-logic state machine, is sampled on
the rising edge of TCK.
TMS is connected high internally and can be left disconnected.
JTAG Controller Reset Input.
TRST is used to reset the JTAG controller.
TRST is connected high internally and can be left disconnected.
• AT2 is the JTAG analog output test port.
• AT1 is the JTAG analog input test port.
Figure 17, “Analog Test Port Application” on page
Section 9.4.2, “Analog Port Scan Register (ASR)” on page 94
95.
Figure 15, “JTAG Architecture” on page
Signal Description
Signal Description
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
93.
86. and