DJLXT384LE Intel, DJLXT384LE Datasheet - Page 48

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
6.3
6.3.1
6.3.2
48
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Receiver
The LXT384 Transceiver has eight identical receivers.
Receiver Clocking
In the receive mode, clocking for the LXT384 Transceiver receiver depends on the following.
When the LXT384 Transceiver is in:
For more information on data-recovery mode, see
Receiver Inputs
A receiver processes input signals as follows:
1. Through the line interface step-down transformer, typically from either a twisted-pair or a
2. The receiver inputs, RTIP (receives positive pulses) and RRING (receives negative pulses),
3. The peak detector samples a received signal and determines its maximum peak value.
4. The peak detector sends a percentage of the maximum peak value to the data slicers. This
•
•
•
Clock-recovery mode, the RCLK pin provides the recovered clock from the signal received at
RRING and RTIP.
Clock-recovery mode with LOS conditions, at the RCLK output there is a transition from
RCLK (derived from recovered data) to MCLK. For more information on clock-recovery
mode, see
Clocking”.
Data-recovery mode and MCLK is:
coaxial cable. (For transformer specifications, see
Unit Circuit
receiver section of the LXT384 Transceiver.
are processed through the internal differential amplifier. The differential amplifier then sends
the signal to the peak detector.
Recovered data is output at RPOS and RNEG in bipolar mode, or at RDATA in unipolar mode.
The recovered clock is output at RCLK. Use the CLKE pin to select the RPOS/RNEG
validation relative to the polarity of the edge of RCLK.
The receiver can:
Regardless of received signal level, the peak detectors are held above a minimum level of
0.150 V (typical), to provide immunity from impulsive noise.
percentage acts as a threshold level to ensure an optimum signal-to-noise ratio. The threshold
level is typically 50% for E1 applications (see
Receive Transmission Characteristics” on page
Table 64, “Intel® LXT384 Transceiver T1 Receive Transmission Characteristics” on
page
— Low, the RCLK pin is in a high-impedance tristate.
— High, the RNEG and RPOS pins are internally connected to an EX-OR output to RCLK
— accurately recover signals in excess of 12 dB of attenuation
— receive signal levels well below 500 mV.
for external clock-recovery applications.
104).
Section 6.3.3, “Receiver Loss-Of-Signal Detector”
Specifications”.) After the transformer, the signal is terminated and is sent to the
Section 6.3.4, “Receiver Data Recovery
Table 63, “Intel® LXT384 Transceiver E1
103) or 70% for T-1 applications (see
Figure 6
and
and
Chapter 12.0, “Line-Interface-
Section 6.3.1, “Receiver
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
Mode”.