DJLXT384LE Intel, DJLXT384LE Datasheet - Page 26

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
26
Table 7.
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Microprocessor-Standard Bus and Interface Signals (Sheet 3 of 3)
ACK /
SDO
RD / R/W/
LEN1
ALE / AS /
SCLK/LEN2
DS /
LEN0
ACK / RDY /
SDO
DS / SDI / WR/
LEN0
1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain
Signal
Name
SDI
RDY
/ WR/
/
QFP
Pin
83
85
86
84
83
84
PBGA
Ball
K14
K14
J13
J12
J14
J14
Signal
Type
DO
DO
DI
DI
DI
DI
Ready Output.
When the LXT384 Transceiver is in the Host Processor mode
using an Intel
NOTE: RDY goes into a high-impedance tristate after
For other pin functions, see ACK and SDO.
Read/Write Input (Write Is Active Low).
When the LXT384 Transceiver is in the:
For other pin functions, see RD.
Shift Clock Input.
When SCLK is in the:
For other pin functions, see AS and ALE.
Serial Data Input.
When the LXT384 Transceiver is in the:
For other pin functions, see DS and WR.
Serial Data Output.
When the LXT384 Transceiver is in the Host Processor mode
using a serial interface and the signal on CLKE is:
NOTE: SDO goes into a high-impedance tristate during a serial
For other pin functions, see ACK and RDY.
Write Enable Input.
When the LXT384 Transceiver is in:
For other pin functions, see DS and SDI.
• Low, RDY indicates a data transfer operation is in progress.
• High, RDY indicates a register-access operation is
• Host Processor mode using a Motorola processor, R/W
• Hardware mode, R/W must be connected to ground.
• Host Processor mode using a serial interface, SCLK acts as
• Hardware mode, SCLK must be connected to ground.
• Host Processor mode using a serial interface, SDI is used as
• Hardware mode, SDI must be connected to ground.
• Low, SDO is valid on the falling edge of SCLK.
• High, SDO is valid on the rising edge of SCLK.
• Host Processor mode using an Intel
• Hardware mode, WR must be connected to ground.
completed.
functions as a read/write signal.
a serial shift clock.
serial data input.
a write enable.
completion of a bus cycle.
port write access.
®
processor and the signal on RDY is:
Signal Description
Revision Date: November 28, 2005
®
processor, WR acts as
Document Number: 248994
Revision Number: 005