DJLXT384LE Intel, DJLXT384LE Datasheet - Page 72

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
7.4.1.1
7.4.1.2
72
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LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Host Processor Mode - Parallel Interface, Motorola* Processor
The Motorola processor interface is selected by asserting the LXT384 Transceiver MOT/INTL pin
low. The R/W signal indicates if a data transfer is to be a read or write. The DS signal is the timing
reference for all data transfers and typically has a duty cycle of 50%. When the Motorola processor
attempts to:
When a Motorola processor is used, CS and DS can be connected. Both read and write cycles
require the CS signal to be low and the Motorola processor to actively drive the address pins. The
LXT384 Transceiver supports a:
Host Processor Mode - Parallel Interface, Intel
The Intel
high. Both the read and write cycles require CS to be low. When the Intel
The LXT384 Transceiver supports a:
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Read data from the LXT384 Transceiver, it asserts R/W high on the falling edge on DS, and
the LXT384 Transceiver drives the data bus.
Write data to the LXT384 Transceiver, it asserts R/W low on the rising edge on DS, and the
Motorola processor drives the data bus.
Non-multiplexed Motorola processor parallel interface when MUX is asserted low. In non-
multiplexed mode, the falling edge of DS is used to latch the address information on the
address bus, and AS must be connected high.
Multiplexed Motorola processor parallel interface when MUX is asserted high. The address on
the multiplexed address data bus is latched into the LXT384 Transceiver on the falling edge of
AS.
Read data from the LXT384 Transceiver, it asserts RD low while WR is held high.
Write data to the LXT384 Transceiver, it asserts WR low while RD is held high.
Non-multiplexed Intel
multiplexed mode, ALE must be connected high and the address and data lines are separate.
Multiplexed Intel
mode, the falling edge of ALE latches the address.
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processor interface is selected by asserting the LXT384 Transceiver MOT/INTL pin
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processor parallel interface when MUX is asserted high. In the multiplexed
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processor parallel interface when MUX is asserted low. In non-
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Processor
Revision Date: November 28, 2005
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processor attempts to:
Document Number: 248994
Revision Number: 005